Systems Day - 2025
Computer Science and Automation, IISc
Computer Science and Automation, IISc
University of Florida, USA
Prabhat Mishra is a Professor in the Department of Computer and Information Science and Engineering at the University of Florida, USA. He is also a Kotak Mahindra Bank’s Visiting Chair Professor at the Kotak IISc AI-ML Centre. He is an IEEE Fellow, a Fellow of the American Association for the Advancement of Science, and an ACM Distinguished Scientist.
Title of the Talk : Explainable AI for Cybersecurity
Abstract of the talk : This talk will provide a comprehensive overview of security attacks as well as detection techniques using explainable AI. First, I will outline a wide variety of software and hardware security threats and vulnerabilities. Next, I will introduce explainable AI algorithms to interpret machine learning behaviors in a human-understandable way, using model distillation, Shapley value analysis, and integrated gradients. I will discuss state-of-the-art attack detection methods using explainable AI. I will also cover how to enable hardware acceleration of explainable AI models for real-time vulnerability detection. Finally, I will discuss the security threats toward machine learning models, and effective countermeasures to design robust AI models.
IIT Guwahati
Dr. John Jose is an Associate Professor in Department of Computer Science & Engineering, Indian Institute of Technology Guwahati, where he joined as an Assistant Professor in 2015. He completed his Ph.D degree from Indian Institute of Technology Madras in the field of computer architecture. He is the recipient of the prestigious Qualcomm Faculty Award 2021 and COMSYS Young Achiever Award 2024 for his teaching, research and outreach education contributions in the field of computing systems. He served as the Vice-Chair of IEEE India Council for a period of 3 years. He is also the core committee member for VLSI Society of India, North-East India chapter. His research group in Multicore Architecture and Systems Lab at IIT Guwahati explores the domain of on-chip communication and memory management techniques for large multicore systems, IoT/embedded system security, hardware accelerators for AI and ML applications, disaggregated storage systems and communication support for future quantum cores. He is the investigator for several R&D projects under DST and MeitY. He is associated with many national pilot projects like NPTEL-MOOCS, SPARC, GIAN, TEQIP etc. He has also served as the associate editor for IEEE-Embedded System Letter Journal from 2022 to 2024. He has over 60 IEEE & ACM peer reviewed conference publications, over 25 ACM & IEEE transactions papers as well as Springer and Elsevier journal papers to his credit.
Title of the Talk : Zero Pollution Prefetcher for Multicore Systems
Abstract of the talk : Data prefetching efficiently reduces the memory access latency in NUCA architectures as the Last Level Cache (LLC) is shared and distributed across multiple cores. But cache pollution generated by prefetcher reduces its efficiency by causing contention for shared resources such as LLC and the underlying network. The talk proposes Zero Pollution Prefetcher (ZPP) that eliminates cache pollution for NUCA architecture. For this purpose, ZPP uses L1 prefetcher and places the prefetched blocks in the data locations of LLC where modified blocks are stored. Since modified blocks in LLC are stale and request for such blocks are served from the exclusively owned private cache, their space unnecessary consumes power to maintain such stale data in the cache. The benefits of ZPP are (a) Eliminates cache pollution in L1 and LLC by storing prefetched blocks in LLC locations where stale blocks are stored. (b) Insufficient cache space is solved by placing prefetched blocks in LLC as LLCs are larger in size than L1 cache. This helps in prefetching more cache blocks, thereby increasing prefetch aggressiveness. (c) Increasing prefetch aggressiveness increases its coverage. (d) It also maintains an equivalent lookup latency to L1 cache for prefetched blocks. Experimentally it has been found that ZPP increases weighted speedup by 2.19x as compared to a system with no prefetching while prefetch coverage and prefetch accuracy increases by 50%, and 12%, respectively compared to the baseline
IIT Roorkee
Dr. Sparsh Mittal is currently working as an associate professor in the ECE department at IIT Roorkee, India. He received the B.Tech. degree from IIT, Roorkee, India, and the Ph.D. degree from Iowa State University (ISU), USA. He has published more than 120 papers at top venues and has nearly 9000 citations. He has received best paper awards or honorable mentions at AIMLSystems, VLSID and ICPR. His research interests are AI for computer vision, applications of AI, computer architecture and VLSI.
Title of the Talk : VADF: Versatile Approximate Data Formats for Energy-Efficient Computing
Abstract of the talk : Previous approximate storage techniques do not consider the possibility of soft errors or malicious bit-flips in AC systems. These errors may interact with approximation-introduced errors in unforeseen ways, leading to disastrous consequences. We present a novel storage format named Versatile Approximate Data Format (VADF) for storing approximate integer numbers while providing resilience to soft errors. VADF prescribes rules for storing, for example, a 32-bit number in either 8-bit, 12-bit or 16-bit numbers. VADF identifies the MSV bit and stores a certain number of bits following the MSV bit. It also stores the location of the MSV bit and protects it by ECBs. VADF does not explicitly store the MSB bit itself and this prevents VADF from accruing significant errors. On image-processing and machine-learning applications, VADF provides higher application quality than previous works in the presence and absence of soft errors. Also, VADF allows the use of narrow arithmetic units.
IIT Ropar
Dr. Venkata Kalyan Tavva (Kalyan) is an assistant professor in the Dept. of CSE, IIT Ropar. He is also an associate faculty of Center of Research for Energy Efficiency and Decarbonization (CREED). Earlier he was a Hardware Performance Architect in the POWER systems performance team, part of India Systems Development Lab, IBM India Pvt. Ltd. Bangalore. He is recipent of the 2022 Qualcomm Faculty Award for his research contributions to the area of memory systems. He has 10 patents to his name and 18 publications in IEEE/ACM journals and conferences. Kalyan works in all the levels of memory hierarchy, i.e., cache, DRAM and SSD; in their redesign for performance and security. In addition he works in high performance graph analytics on GPUs. Kalyan received his PhD from IIT Madras. He is a member in IEEE and ACM.
Title of the Talk : A Walk Down the Memory Lane - Cache, NVM, DRAM and SSD
Abstract of the talk : In this talk, we will go through various problems in Cache, NVMs, DRAM and SSDs both from performance and security perspectives. We'll dive into a few solutions proposed by our Computer Architecture - Special Interest Group (CA-SIG) team at IIT Ropar.
IISc Bangalore
Komondoor V Raghavan is an Associate Professor at the Department of Computer Science and Automation (CSA), Indian Institute of Science (IISc), Bangalore. He obtained his Bachelors degree from Govt. College of Technology, Coimbatore, Masters degree from IIT Bombay, and PhD degree from Univ. of Wisconsin-Madison. His areas of interest are program analysis, programming tools, and formal methods for software engineering. His group has developed several cutting-edge open-source tools to support development of correct and efficient programs.
Title of the Talk : Kondo: Efficient Provenance-Driven Data Debloating
Abstract of the talk : Isolation increases upfront costs of provisioning containers. This is due to unnecessary software and data in container images. While several static and dynamic analysis methods for pruning unnecessary software are known, less attention has been paid to pruning unnecessary data. In this paper, we address the problem of determining and reducing unused data within a containerized application. Current data lineage methods can be used to detect data files that are never accessed in any of the observed runs, but this leads to a pessimistic amount of debloating. It is our observation that while an application may access a data file, it often accesses only a small portion of it over all its runs. Based on this observation, we present an approach and a tool Kondo, which aims to identify the set of all possible offsets that could be accessed within the data files over all executions of the application. Kondo works by fuzzing the parameter inputs to the application, and running it on the fuzzed inputs, with vastly fewer runs than brute force execution over all possible parameter valuations. Our evaluation on realistic benchmarks shows that Kondo is able to achieve 63% reduction in data file sizes and 98% recall against the set of all required offsets, on average.
IIT Bombay
A mortal who is excited about microarchitecture and in general computer architecture research. A micro-architect does all the heavy lifting to squeeze out the best performance out of applications running on computing systems. Biswa's well-known microscopic contributions are the state-of-the-art high performing cache compressors and multi-level hardware data prefetchers. Biswa is one of the recipients of Qualcomm India Faculty Award 2022, Google India Research Award 2022, Prof. Krithi Ramamritam Award for creative research 2023, and Qualcomm Faculty Award 2024.
Title of the Talk : Obvious is definitely not obvious: Designing High-Performance Storage Efficient and Yet Secure Memory Systems in an Obvious Way
Abstract of the talk : The talk will highlight three recent works on designing secure last-level cache, hardware prefetchers, and DRAM that appeared at ISCA 2024, MICRO 2024, and HOST 2024 respectively. We will mostly focus on obvious designs to optimize conflicting tradeoffs and how to make obvious designs really obvious in the context of design of secure memory systems.
IIT Bhubaneswar
Dr. Debiprasanna Sahoo did his B.Tech. in Computer Science and Engineering from College of Engineering and Technology Bhubaneswar (now OUTR). He further went on to complete his M.Tech. in Computer Science and Engineering from Indian Institute of Technology Madras (IITM). He pursued his Ph.D. from Indian Institute of Technology Bhubaneswar (IIT-BBS). His research interests include Computer Architecture particularly related to performance and verification aspects caches and memory. He worked as an Assistant Professor at the Indian Institute of Technology Roorkee (IITR). Dr. Debiprasanna Sahoo has also worked as a Member of Technical Staff Silicon Design Engineer at Advanced Micro Devices (AMD); he worked towards the development of current generation AMD Ryzen/EYPC processors.
Title of the Talk : Modeling and Performance Opportunities on 3D Stacked Last Level Caches
Abstract of the talk : In this talk, he is going to discuss about the accurate modeling of a 3D Stacked network and caches in modern CPUs and GPUs. He will also briefly discuss about the performance aspects of the 3D Stacked L3 Cache.
IIT Bhubaneswar
Dr. Devashree Tripathy is an Assistant Professor in Computer Science and Engineering at Indian Institute of Technology, Bhubaneswar. Her research spans in Computer Architecture , Machine Learning, Hardware/Software codesign of AI systems, Energy-Efficient computing, Sustainable AI, TinyML, and Systems for Healthcare, Drones, Autonomous Cars and Robotics, Mobile and Edge Computing. Her current research focuses on ML for Systems and Systems for ML. Prior to joining IIT Bhubaneswar, Dr. Tripathy was a Postdoctoral Fellow in Computer Science at Harvard University in Harvard Architecture, Circuits, and Compilers Group. She is currently working as an Associate with Harvard University. She graduated from University of California, Riverside with PhD in Computer Science.
Title of the Talk : AI Infrastructure: Optimizing LLM for Efficiency and Scalability
Abstract of the talk : Large Language Models (LLMs) are revolutionizing AI applications with their unprecedented language understanding and generation capabilities. However, training and deploying these models at scale can be computationally expensive and resource intensive. To unlock the full potential of LLMs, it is crucial to optimize their inference process. This talk will delve into various techniques to optimize LLM inference, focusing on striking a balance between latency and throughput. We will explore strategies to address key challenges such as memory contention, large model size, and low throughput. By leveraging deep domain knowledge of AI/ML workloads, we can design and improve the efficiency of LLM systems.