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Jayant Haritsa
Professor, CDS and CSA, IISc Bangalore
Jayant Haritsa is with the CDS and CSA departments at the Indian Institute of Science, Bangalore, since 1993. He received a BTech degree from the Indian Institute of Technology (Madras), and MS and PhD degrees from the University of Wisconsin (Madison). He is a Fellow of ACM and IEEE.
Title of the talk: Exposing Malicious Database Queries
Abstract of the talk: We have recently defined a new query reverse-engineering problem of unmasking SQL queries hidden within opaque database applications. The diverse industrial use-cases for this problem range from enterprise data security to query rewriting. It poses hard and novel intellectual challenges due to the presence of a variety of complexities such as dependencies between the query clauses, schematic renaming in the output attributes, result consolidation due to aggregates, and presence of computed column functions. In this talk, we motivate the hidden query extraction problem, and then present UNMASQUE, an extraction algorithm based on an active learning approach, that successfully exposes a complex class of hidden warehouse queries.
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Hemangee K. Kapoor
Professor, CSE, IIT Guwahati
Hemangee K. Kapoor is a Professor in the Department of Computer Science and Engineering at Indian Institute of Technology Guwahati, India. She received her B.Eng. degree in Computer Engineering from the College of Engineering, Pune, India, M.Tech. degree in CSE from the IIT Bombay, and Ph.D. degree in CSE from London South Bank University, U.K.
Her research interest spans the broad area of computer architecture and specifically in multicore caches, emerging non-volatile memory technologies, network-on-chip and design of accelerators for neural networks. She has published at reputed venues and has supervised 8 PhD theses and 80+ BTech/Mtech projects till date, with several students currently doing research in her group. Her research has been supported by the Department of Science and Technology, the Department of Electronics/ Ministry of Communication and Information Technology and Intel. She is a Senior Member of the IEEE and ACM.
She is Associate Editor on Journal of Systems Architecture (Elsevier) and IEEE Design and Test. Prof. Kapoor has actively participated in the ACM India council: as a member (2014-22) and as Vice President (2020-22). She also serves as a member on the ACM international council for Diversity, Equity and Inclusion (ACM-DEI) (2021-25).
Title of the talk: Emerging Non-Volatile Memories: Challenges and Research Directions
Abstract of the talk: Increased transistor density and processing capacity need high density memories. Given that conventional SRAM/DRAM are not scalable, emerging non-volatile memory (NVMs) are thought to be potential substitutes. NVMs can provide high density with low leakage power. However, low write durability, high write latency, and high write energy hinder their adoption as complete replacements for SRAM/DRAM. In this talk we will see techniques to improve NVM longevity. The repetitive writes carried out in the NVM cells cause their early wear out since NVM writes are significantly more expensive than reads in terms of energy and latency. To extend the lifetime of NVMs, techniques have been developed for both reducing write and distributing writes. Techniques for reducing the number of writes to the NVM cell include compression and encoding. The writes are distributed among various cells using wear-leveling techniques.
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Gopalakrishnan Srinivasan
Assistant Professor, CSE, IIT Madras
Gopal received his B.Tech. in Electrical and Electronics Engineering from the National Institute of Technology Calicut, in 2010. He subsequently received his Master’s in Computer Engineering from North Carolina State University, Raleigh, NC, in 2012, and PhD in Electrical Engineering from Purdue University, West Lafayette, IN, in 2019. He is currently an Assistant Professor in the department of Computer Science and Engineering at IIT Madras. His research entails developing bio-plausible (neuromorphic) machine learning algorithms and hardware architectures for energy-efficient computing at the edge. His doctoral dissertation proposed brain inspired spiking neural network architectures (convolutional and recurrent) and learning methodologies (unsupervised, supervised, and semi-supervised) for image and speech recognition applications. His doctoral research on stochastic spiking neural network and its energy-efficient hardware realization was covered in press by the Purdue Research Foundation, Tech Xplore, and ScienceDaily.
Gopal also had a distinguished career in industry prior to venturing into academia. He started his career (after obtaining his Master’s) as a Digital Design Engineer in Cirrus Logic, Austin, TX, where he was involved in the design and verification audio ICs. During his PhD, he interned with the ASIC and VLSI Research group at Nvidia, where he worked on the design of digital modules using object-oriented SystemC/ C++. Post his PhD, he joined MediaTek as a Staff Engineer, where he was involved in architecture pathfinding, performance modeling, and RTL design of the next generation of deep learning accelerator. He then moved to Apple as a Machine Learning Platform Architect, where he carried out architecture research and performance modeling of the Apple Neural Engine to efficiently accelerate machine learning workloads. He subsequently moved to India and joined Mindgrove Technologies, which is a startup specializing in building RISCV-based SoCs. He currently serves as their lead architect and consultant, where he is responsible for driving the design of a multicore SoC targeting computer vision applications.
Title of the talk: Energy-Efficient Neuromorphic Computing using Spiking Neural Networks
Abstract of the talk: Spiking Neural Networks (SNNs), widely regarded as the third generation of artificial neural networks, offer a plausible solution to approaching the brains’ processing capability for cognitive tasks. With biologically realistic perspective on input processing, SNN performs neural computations using spikes in an event-driven manner. The spike-based asynchronous computing capability can be exploited to achieve improved energy efficiency in neuromorphic hardware implementation. In this talk, I will describe our work on different SNN training methods, namely, Spike Timing Dependent Plasticity (STDP), ANN-SNN conversion, and spike-based backpropagation (using surrogate gradient for the discontinuous spiking neuron derivative). The efficacy of the proposed methods are demonstrated for state-of-the-art deep SNNs.
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Radhika B S
Assistant Professor, CSE, NIT Karnataka, Surathkhal
Dr. Radhika is an Assistant professor in the Department of Computer Science and Engineering at the National Institute of Technology Karnataka Surathkal (NITK). She has done her PhD from the Indian Institute of Technology Bombay. Her research interests include Operating System Security, and Access Control.
Title of the talk: Access Management: Safeguarding Digital Assets and Enhancing Security
Abstract of the talk: In this digital era regulating access to data plays a crucial role in providing security and privacy. The talk focuses on basics of security, significance of access management, and a few existing solutions.
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Jayashree Mohan
Senior Researcher, Microsoft Research
Jayashree Mohan is a Senior Researcher at Microsoft Research Bangalore working primarily on building efficient AI infrastructure, with a current focus on LLM serving. Prior to joining MSR, Jayashree received a PhD in Computer Science from the University of Texas at Austin, where her dissertation focused on optimizing storage for ML workloads.
Title of the talk: Large Language Models : Efficient scheduling and deployment
Abstract of the talk: Large Language Models (LLMs) have revolutionized various domains by performing tasks requiring human-like skills. However, efficiently scheduling and deploying these models at scale remains a significant challenge . This talk will provide an overview of LLMs, focusing on the scheduling and deployment challenges and how recent research addresses these issues. First, we will discuss the background of LLMs, highlighting their importance and the complexities involved in their inference process . We will then delve into the scheduling challenges faced during LLM inference, particularly the throughput-latency tradeoff . The talk will discuss Sarathi-Serve, an efficient LLM inference scheduler, which addresses this tradeoff by introducing chunked-prefills and stall-free schedules. Finally, we will explore the large-scale deployment challenges of LLMs, including the optimization of various configuration options such as model parallelization strategies, batching algorithms, and scheduling policies . We will present Vidur, a large-scale simulation framework, which helps identify optimal configurations for LLM deployment by simulating performance across a wide range of system settings.
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Vaishnavi Sundararajan
Assistant Professor, CSE, IIT Delhi
Vaishnavi Sundararajan is a Chandruka New Faculty Fellow and Assistant Professor in the Department of Computer Science and Engineering at the Indian Institute of Technology Delhi. She is also associated with the Center of Excellence in Cyber Systems and Information Assurance (CSIA). Her main interests lie in the application of formal methods and logic to various fields, primarily security. Vaishnavi completed her PhD at the Chennai Mathematical Institute, and after her PhD, has worked at CNRS (IRISA), Ericsson Research, and at UC Santa Cruz.
Title of the talk: Can Sherlock Holmes Defeat a Hacker?
Abstract of the talk: Security protocols are all around us, now that most of our lives are digital, whether it be for banking, healthcare, communication, or entertainment. This brings up issues of security and privacy wrt our data that we give to service providers. Can a malicious entity get a hold of our information, in spite of the best cryptographic primitives being used? This talk seeks to address that question, and to show how we can use deductive analysis to pre-emptively detect the possibility of such behaviour.
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Jyothi Vedurada
Assistant Professor, CSE, IIT Hyderabad
Jyothi Vedurada is an assistant professor at the Dept. of Computer Science and Engineering, IIT Hyderabad. Her research interests are compilers, program analysis, and high-performance computing. Prior to joining IIT Hyderabad, she was a post-doctoral researcher at Microsoft Research Lab, Bangalore. She received her PhD (+M.Tech) from IIT Madras, supported by the TCS PhD fellowship. She received Google Research exploreCSR Award 2021, Distinguished Paper Award at OOPSLA 2021, Distinguished Reviewer Award for OOPSLA 2019 Artifact Evaluation PC, and Institute Research Award for her PhD thesis.
Title of the talk: BANG: Billion-Scale Approximate Nearest Neighbour Search using a Single GPU
Abstract of the talk: In today’s data-driven world, the need to quickly search through vast amounts of high-dimensional data is more crucial than ever. Approximate Nearest Neighbor Search (ANNS) plays a key role in applications like information retrieval, pattern recognition, and image processing. This talk presents a new approach to scaling ANNS on GPU for massive datasets beyond traditional limits. By managing data efficiently and harnessing GPU's computational power, we achieve faster, more efficient search results (than current state-of-the-art approaches) without sacrificing accuracy. I will also share ongoing work in our group on optimizing CPU-GPU programs through advanced compiler techniques to improve synchronization and performance.
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Jayesh Gaur
Principal Engineer, CPU Research, Intel
Jayesh Gaur is a principal engineer in Processor Architecture Research Lab, Intel Labs, India. He is an expert cpu and memory architect and has led advancements in cpu architecture for multiple generation of Intel mainstream P core processors. He has about 60 US patents filed in cpu architecture and 20+ publications in top architecture conferences. He is the recipient of best paper awards at HPCA 2017 and at ISCA 2024. Jayesh has also been admitted to the Hall of Fame of the International Symposium on computer architecture (ISCA). He completed his education at the Indian Institute of Technology, Kanpur and at the University of Michigan, Ann Arbor.
Title of the talk: Challenges in advancing general purpose CPU computing
Abstract of the talk: CPU performance scaling has been slowing down over generations. This talk with cover an industry perspective on what are the primary areas that are limiting CPU performance. What challenges exist in advancing CPU performance, and the areas that need urgent research attention.
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Ranjita Bhagwan
Principal Engineer, Google Global Network
Ranjita Bhagwan is currently a Principal Engineer at Google, working on making Google's network highly reliable. Prior to this, she was a Senior Principal Researcher at Microsoft Research India where she worked for more than a decade on applying machine learning to improve system reliability, security and performance. Recently, her work has focused on using data-driven approaches to improve networks and services and has led to several publications and awards. She is an ACM Distinguished Member, INAE Fellow, and is the recipient of the 2020 ACM India Outstanding Contributions to Computing by a Woman Award. She received her PhD and MS in Computer Engineering from University of California, San Diego and a BTech in Computer Science and Engineering from the Indian Institute of Technology, Kharagpur.
Title of the talk: Providing High Reliability in the Google Global Network
Abstract of the talk: Google owns and operates one of the world's largest networks, supporting billions of users. Today, this network not only supports the users of Google's various applications such as Search, Youtube, Gmail and Maps, it also forms a critical part of the infrastructure supporting enterprise customers of the Google Cloud Platform. Given the scale and the challenging requirements of such varied applications, the network incorporates many aligned but complementary techniques to ensure high network reliability. In this talk, I will describe some of these techniques, and how they work in tandem to provide a high-reliability network to all of Google's users.
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Urbi Chatterjee
Assistant Professor, IIT Kanpur
Urbi Chatterjee is an Assistant Professor in the Department of Computer Science and Engineering, Indian Institute of Technology Kanpur. She received her MTech degree fromIIT_ISM Dhanbad in 2013 and PhD from IIT Kharagpur in 2020. She has also worked in industry for one and half years. Her broad area of research is Hardware Security. She currently works on Physically Unclonable Functions, Security Analysis of Approximate Computing Hardware, Timing Side Channel attacks on Network-on-Chip Architecture, Acoustic Side Channel attacks etc.
Title of the talk: The Present and Future of Hardware Security for Embedded Systems
Abstract of the talk: In the past decade, the field of hardware security has grown into a major research topic, attracting intense interest from academics, industry and governments alike. Currently, under the initiate of “Make-in-India”, a drive has been taken to develop, manufacture, and assemble semiconductor products made in India and incentivize dedicated investments into manufacturing. With the demand for electronic hardware expected to rise rapidly, India has the potential to become an electronic manufacturing hub. However, as with most emerging technologies, innovation is prioritized, and security is an afterthought in response to discovered vulnerabilities. In this talk, we are going to bridge this gap and highlight some key findings that can impact the security aspects of embedded systems. We will start with how a simple stethoscope can disassemble the instructions running on a simple Arduino board mounting ATmega328P microcontroller or a Raspberry Pi consisting of ARM processor using acoustic side channel analysis (SCA). These devices are widely used in edge computing and industrial applications, hence pose immense threats against acoustic SCA. Subsequently we will delve into our our contributions in timing SCA on network-on-chip architecture which is coming up as an emerging network-based communications subsystem in Multiprocessor System-on-Chips. The talk will then shifts to approximate hardware circuits that are widely used now-a-days in ML/AI accelerators and show how digital Hardware Trojan Horses can exploit the probabilistic nature of approximate designs to reduce the end applications accuracy drastically. And finally, we will quickly discuss how the desperate attempts to make the delay based physically unclonable functions (PUFs) using challenge-response obfuscation can be dimished by intelligent crafting of challenges to train the ML tools and build a soft model of the targetted PUF architecture.
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Sameer G. Kulkarni
Assistant Professor, IIT Gandhinagar
Sameer G Kulkarni is an Assistant Professor in the Departments of Computer Science and Engineering, and Electrical Engineering at Indian Institute of Technology, Gandhinagar. Prior to this, he worked as a postdoctoral researcher at the University of California, Riverside. He received a Ph.D. degree in Computer Science from University of Göttingen, Germany in July 2018. He received his M.S. degree in Computer Engineering from the University of Southern California, in 2010, and B.E. degree in Computer Science and Engineering from National Institute of Engineering, Mysore, in 2004. He is the recipient of the IEEE TCSC Best PhD Dissertation Award 2019. His work focuses on the resource management aspects towards building Efficient, Scalable and Resilient NFV/Edge platforms. His research interests include Software Defined Networking, Network Function Virtualization, Edge Cloud Platforms, Distributed systems, and Disaster Management.
Title of the talk: NFV and Edge Cloud for Efficient Machine Learning and Security Services
Abstract of the talk: In this talk, I will present our work D-Stack - a high throughput DNN Inferencing by effective multiplexing and spatio-temporal Scheduling of GPUs and GSLICE - a DPDK based NFV framework for Inferencing . GSLICE incorporates a dynamic GPU resource allocation and management framework to maximize performance and resource utilization. We virtualize the GPU by apportioning the GPU resources across different Inference Functions (IFs), thus providing isolation and guaranteeing performance. We develop controlled spatial sharing of GPU, self-learning and adaptive GPU resource allocation and batching schemes that account for network traffic characteristics, while also keeping inference latencies below service level objectives. GSLICE adapts quickly to the streaming data’s workload intensity and the variability of GPU processing costs. GSLICE provides scalability of the GPU for IF processing through efficient and controlled spatial multiplexing, coupled with a GPU resource reallocation scheme with minimal (less than 100 microseconds) downtime. Compared to TensorRT and default MPS, GSLICE significantly improves GPU utilization efficiency and achieves 2-13x improvement in aggregate throughput.
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Sathish Vadhiyar
Professor, IISc, Bangalore
Sathish Vadhiyar is Professor in the Department of Computational and Data Sciences and Chair of Supercomputer Education and Research Centre, Indian Institute of Science. He obtained his B.E. degree in the Department of Computer Science and Engineering at Thiagarajar College of Engineering, India in 1997 and received his Masters degree in Computer Science at Clemson University, USA in 1999. He graduated with a PhD in the Computer Science Department at University of Tennessee, USA in 2003. His research areas are in HPC application frameworks including multi-node and multi-device programming models and runtime strategies for irregular applications including graph applications and AMR applications, performance characterization and scalability studies, processor allocation, mapping and remapping for large scale executions, middleware for production supercomputer systems, and fault tolerance for parallel applications. He has also worked with applications in climate science and visualization in collaboration with researchers working in these areas. Dr. Vadhiyar is a senior member of IEEE, professional member of ACM, and has published papers in peer-reviewed journals and conferences. He was the program co-chair of HPC area in HiPC 2022, chair of senior member award committee of ACM, was an associate editor of IEEE TPDS, and served on the program committees of conferences related to parallel and grid computing including IPDPS, IEEE Cluster, CCGrid, ICPP, eScience and HiPC. Dr Vadhiyar is also an investigator in the National Supercomputing Mission (NSM), a flagship project to create HPC ecosystem in India, where he manages the R&D projects related to HPC in the country.
Title of the talk: Divide-and-Conquer Paradigm for Asynchronous CPU-GPU Computations in Graph and AI/ML Applications
Abstract of the talk: As High Performance Computing (HPC) is in the Exascale era, it presents exciting opportunities to leverage large number of CPU and GPU processing cores for fast executions of large-scale applications. However, efficient utilization of exascale systems presents challenges to programmers including avoiding global synchronizations and heavy communications. Asynchronous models of executions will have to be developed to provide scalability for a large number of cores. This talk will cover the use of divide-and-conquer model to provide such asynchronous executions in two important class of applications, namely, Graph and of course, AI applications. In graph applications, we have developed hybrid CPU-GPU asynchronous strategies for Boruvka's MST and Louvain's community detection algorithms. For AI applications, we propose a novel divide-and-conquer model of parallelism that provides less synchronizations and has potential for high scalability when compared to the existing data and pipleline parallelism models. Our strategies have resulted in 20-80% performance improvements over existing state-of-art works.
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Mythili Vutukuru
Associate Professor, IIT Bombay
Mythili Vutukuru is an Associate Professor at the Department of Computer Science and Engineering at IIT Bombay. Before joining IITB in 2013, she obtained her M.S. and Ph.D. degrees in Computer Science from the Massachusetts Institute of Technology in 2006 and 2010 respectively. After her Ph.D., she worked at Movik Networks, a startup in the telecom space, for 3 years before joining IITB. Earlier, she obtained a B.Tech. degree in Computer Science and Engineering from the Indian Institute of Technology, Madras in 2004. She is passionate about working on real-world problems in the broad area of networked systems.
Title of the talk: Understanding the internals of the Linux network stack
Abstract of the talk: In this talk, we will do a deep drive into the internals of the Linux network stack. We will understand everything that happens when you send or receive packets on a computer system, and trace the journey of the packet from the device driver all the way to the application. We will also understand the limitations of the network stack in keeping up with the high speeds of modern network links, and briefly discuss various new ideas being proposed to improve the network stack performance.
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Suparna Bhattacharya
Fellow, AI Research Lab, HPE
Suparna Bhattacharya is an HPE Fellow in the AI Research Lab at Hewlett Packard Labs, with a focus on Data-centric Trustworthy AI and Foundation Models research and deep experience in several areas of systems software and data-processing systems. This includes several open-source contributions to the Linux kernel, 32 granted patents, 36 publications and a book on Resource Proportional Software Design for Emerging systems. Prior to joining HPE in 2014, Suparna worked at IBM Research Labs and IBM Systems Technology Labs in India. Suparna is an IEEE Fellow, a Fellow of the Indian National Academy of Engineering, a Distinguished Alumnus of IIT Kharagpur and a recipient of several awards including IEEE India Council Women Technologist of the year and IISc. Prof S.K. Chatterjee Award for Outstanding Woman Researcher. She holds a B.Tech from IIT Kharagpur (1993) and a late-in-life PhD with a best thesis in Computer Science from IISc (2013).
Title of the talk: Foundation Models as Operating Systems: Expanding System Software Principles to Advance AI
Abstract of the talk: Generative AI based Foundation Models (FMs), including large language models (LLMs) and diffusion models, are profoundly changing the paradigm of how AI is applied across a broad spectrum of use cases. FMs provide a powerful substrate for the next generation of enterprise applications and scientific discovery. However, to fully harness their potential, these models must be continuously augmented with accurate knowledge, their reasoning verified to ensure compliance with underlying expectations, and their execution optimized to meet resource constraints for the desired use case. In this talk, we explore the potential of using mechanisms inspired by operating systems to construct a dynamic and powerful 'virtual' FM substrate. This substrate can evolve over time to address these challenges. We draw parallels from virtualization and OS concepts to enhance the adaptability of FM capabilities, much like the human brain uses different modes and speeds of thinking to adapt to new situations and information.
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Uday Reddy Bondhugula
Professor, IISc, Bangalore
Uday Bondhugula is a professor of computer science at the Indian Institute of Science (IISc), in Bangalore, India, and the founder and CTO at PolyMage Labs. His research interests lie in the areas of high-performance computing, compilers, polyhedral framework, automatic parallelization, and high-performance systems/accelerators for deep learning and artificial intelligence. He received his Ph.D. from the Ohio State University in 2008 and his Bachelor’s in Computer Science from the Indian Institute of Technology, Madras, in 2004. He is the original author and maintainer of Pluto, a source-to-source loop parallelization and optimization tool based on the polyhedral framework. He recently received the ACM SIGPLAN Most Influential Paper award for his PLDI 2008 paper on polyhedral optimization for parallelism and locality. As a visiting researcher at the Google Brain team in 2018, he was a founding team member of the MLIR project.
Title of the talk: Building Compilers for AI Programming Frameworks
Abstract of the talk: Compilers are software systems that translate programming languages into instructions that the hardware can execute, in a manner that realizes the expressed semantics while using the hardware efficiently. This talk will describe the interesting new challenges and opportunities in the field of building compilers for the current wave of programs and computations being developed and used in the Artificial Intelligence domain.
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Kanishka Lahiri
Fellow, Server Performance, AMD
Kanishka Lahiri is currently a Fellow at Advanced Micro Devices working on performance architecture of AMD’s EPYCTM Processors. In his 16 years at AMD he has worked on simulators, workload characterization, SOC architecture, post-silicon bring-up, and performance tools and methodology. Prior to AMD he had a brief, but career-changing stint at Montalvo Systems working on x86 core micro-architecture. He started his career conducting research at NEC Laboratories America. He obtained his PhD from UC San Diego (2003), and B.Tech in Computer Science from IIT Kharagpur (1998).
Title of the talk: Performance Analysis of Data Center CPUs
Abstract of the talk: In this talk, we will review the pivotal role performance analysis plays in every stage of the CPU design process. We will go over critical technologies that have been developed over the decades to make chips built out of 100+ billion transistors match performance goals defined years before silicon becomes available. We will review how to do this while meeting the enormous computational challenges posed by this problem. We will also discuss performance benchmarks, and their role compared to real applications and behaviors that we see in the data center.
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Ashish Panwar
Senior Researcher, Microsoft Research
Ashish Panwar is a Senior Researcher at Microsoft Research India where he works in the systems group. He currently spends most of his time thinking about how to optimize the performance of the LLM serving systems. Ashish obtained his PhD in 2022 from the CSA department at IISc.
Title of the talk: From Basics to Breakthroughs: Tales from LLM Systems Research
Abstract of the talk: This talk will emphasize that the most groundbreaking innovations often stem from a deep understanding of fundamental principles. In particular, I will showcase recent advancements in systems research on large language models (LLMs), illustrating how foundational knowledge propels significant technological progress.
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Nanditha Rao
IBM
Nanditha Rao recently transitioned to the logic design team at IBM. She is a recipient of the Fulbright-Nehru Fellowship for 2023-24 and worked at the lab of computer architecture at UT Austin. She was as an Assistant Professor in the VLSI Systems group at IIIT Bangalore and an affiliated researcher with the SAFARI group at ETH Zurich. Her research interests are in the field of computer architecture, processor design, and FPGA accelerators. She completed her PhD from the Department of Electrical Engineering, IIT Bombay in 2017.
Title of the talk: Vector and reconfigurable processing elements to accelerate edge inference on FPGAs
Abstract of the talk: Vector and floating-point (FP) accelerators can significantly enhance the throughput of convolution/matrix multiplications, which are key compute tasks for ML inference. FPGAs are best suited to accelerate such tasks due to their inherent parallel processing capabilities. Vector processing unit involves multiple compute blocks and operates on multiple data elements simultaneously. Reconfigurable processing elements and variable precision floating point units are capable of adjusting the precision dynamically based on the requirements of the computation. We prototype such architectures/designs on an FPGA and further improve their performance by mapping them onto efficient hardware resources on the FPGA fabric. A key challenge will be to assign and dynamically map workloads onto these special accelerators.
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Sanjay Aghara
System Software Architect, Intel
Sanjay is a System Software Architect from Client Computing Group BU of Intel® Corporation, responsible for driving client technologies working with ecosystem partners.
Sanjay joined Intel India in 2011 and have worked on building multiple innovation products and solutions across various domains.
Sanjay holds 3 patents and 2 more are pending.
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